1. Field of the Invention
This invention pertains generally to semiconductor memory, and more particularly to control circuits within dynamic random access memories (DRAMs).
2. Description of Related Art
Dynamic Random Access Memory (DRAM) circuits and devices have been utilized as main memory for servers, personal computers, and a wide range of other electronic devices.
A conventional DRAM comprises arrays of memory cells which each comprise a switching device coupled to a charge storage element as shown in FIG. lA. The switch typically comprises a transistor, such as an NMOS transistor, while the storage device typically comprises a capacitor. The logic state of the cell (“1 ”or “0 ”) is determined with respect to the level of charge stored on the capacitor, for example a “1 ” state is typically represented by the presence of charge, and a “0 ” state by its absence. The switch is activated for writing to the cell, or reading from the cell, and then is switched off so as to retain cell state. It will be recognized that over time the charge stored on the capacitor dissipates as a result of various forms of leakage. At some point in time the charge stored for the “1 ”cell state drops to that of the cells held in the “0 ” state, wherein memory data becomes lost. FIG. 1B depicts a typical sense amplifier section to which bit line pairs SA BL1, SA BLB1 through SA BL256, SA BLB256 are coupled. A CMOS latch portion is shown bounded by a dashed line, with power source and ground source transistors marked.
In response to this leakage, DRAM devices require incorporation of a periodic charge-restoring operation to maintain cell information. These charge-restoration operations are referred to as refresh operations, or cycles, such as performed by a memory controller, and more preferably by an internal memory controller performing what is referred to as self-refresh.
DRAM chips have different current consumption characteristics depending on operating mode. When a word-line is enabled for write or read operation it is in active mode, and in pre-charge state the word-line is disabled. Normally, the current consumption during pre-charge state is less than during active mode and consists of standby current for the DC generator, leakage current in core and peripheral circuits, and current used by circuits that detect changes in the chips operating mode. As chip density increases and process technology shrinks, more leakage paths arise during standby state, such as in the case of micro-bridges, which are created in response to process defects.
Normally, when a micro-bridge arises between a word-line and a bit-line, the corresponding cell cannot be used and the associated row (or column) of memory cells is replaced with another using a redundant row (or redundant column). In response to utilizing this repair cell, the cell density and functionality of the device as originally intended can be maintained. However, during stand-by state, the bit-line of the defective cell is at Vblp level and the word-line is at a certain predetermined stand-by level. Typically, the stand-by level of the word-line is 0V, or less, to keep the NMOS cell access transistor in an off state to maintain cell data. Thus, a leakage path exists between the bit-line and word-line through the micro-bridge. The bit-line level is provided by a Vblp generator, wherein the leakage current flows from the Vblp generator to ground or to the negative bias generator connected to the word-line. Therefore, micro-bridges contribute to increases in standby current and thus indirectly still result in lower factory yields.
A DRAM contains many word-lines, bit-lines, and storage cells which are subject to process defects and variation. As a consequence of these defects and variations, a certain portion of the memory storage cells do not function properly, or have inadequate retention time according to chip specification. Currently, the rows of faulty memory cells cannot be used for write/read functions regardless of whether the row is completely non-functional or merely suffers from insufficient data retention period (less than the specified retention duration).
In order to replace the rows of memory associated with these defective cells, a certain number of redundant (extra) storage cells, redundant word-lines, and redundant bit-lines are built into each DRAM chip to access these spare cells. When using a redundant word-line, the information that enables the redundant word-line is the address of the corresponding defective word-line, and this address, referred to as an X-address, is stored in a physically or electrically programmable fuse.
In conventional memory repair methods, each of these redundant word-lines is only usable for row repair when all of the redundant memory cells contained within the associated row are functional (not defective) and have cell retention times that meet specification. However, like the original rows of memory cells, a portion of these redundant rows are also generally unusable due to retention time issues. Therefore, since the number of redundant rows is limited, a certain proportion of memory chips are not able to be repaired to meet first bin specifications according with these conventional memory repair methods, and thus these chips are either downgraded or disposed of.
Accordingly, a need exists for circuits and methods for reducing self refresh and leakage power consumption while improving self refresh characteristics within memory circuits, and in particular dynamic memory circuits. These needs and others are met within the present invention, which overcomes the deficiencies of previously developed circuits and methods.